EDN

Pulse-latch approach reduces dynamic power

Recently, many methodologies have been introduced for reducing dynamic power for systems-on-chip (SoCs). These methodologies, however, impose restrictive physical constraints which have schedule ...
EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
Electronic Design

Make A Dual ECL Latch Function As A Dual R-S Flip-Flop

The MC1030 is a clocked dual D-type latch. Any change in the D input will be reflected at the output while the clock is low. The outputs are latched on the clock's ...
Design-Reuse

Dual edge sequential architecture capable of eliminating complete hold requirement from the test path

Freescale Semiconductor India Pvt. Ltd. Scannability has always been a challenge and with the complex architectures, challenges gets multifold by imposing several limitations like HOLD closure, yield ...
Ars Technica

help with Logic Circuits and specifically Flip-Flops

I'm trying to help my son understand flip-flops. He's home from Uni for holiday and has a "workbook" to get thru all about Logic Circuits and Boolean algebra etc. Between us we've been able to ...
Design-Reuse

Sequential architecture for absolutely NO hold requirement in the Shift path

Scannability has always been a challenge and with complex architectures, the challenge is exacerbated by imposing several limitations like HOLD closure, yield loss, silicon failures due to HOLD, scan ...